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皇冠登录入口教师——梁洁

创建时间:  2021/03/11  康蕊   浏览次数:   

梁洁 副教授

邮箱:liangjieclair@shu.edu.cn

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导师介绍:

从事皇冠登录入口的先进微纳电子材料、器件、片上先进互连应用的研究,基于SOI的射频器件的研究,可穿戴柔性器件及生物信号放大电路设计等研究。在相关领域发表SCI、EI顶会论文(包括IEDM、Symp. VLSI)20余篇,获得欧盟授权专利2项。主持国家自然科学基金1项。博士期间连续3年参与2项大型欧盟地平线计划H2020项目。2022年3月入选上海市海外高层次人才引进计划。

招收微电子、电子信息、应用物理、材料工程等相关专业背景的硕士。


研究方向:

先进微纳电子器件、先进片上互连应用;碳基微纳电子器件;可穿戴柔性器件及生物信号放大电路设计;SOI射频器件。


教育背景:

2019年博士毕业于法国蒙彼利埃大学微电子学专业

2016年硕士毕业于巴黎大学量子器件学专业

2014年本科毕业于巴黎大学物理学专业


工作经历:

2022年3月-至今 上海大学 副教授

2021年3月-2022年3月 上海大学 讲师、特聘副教授,硕士生导师,担任2020级微电子科学与工程专业2班班导师

2019年8月-2020年12月 新加坡国立大学 博士后


科研成果及获奖情况:

在相关领域发表SCI论文20余篇,获得欧盟授权专利2项。主持国家自然科学基金1项。


近五年代表性论文:

  1. J. Liang, S. Chen, H. Xu, et al. and G. Xiao " Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part II:Comb like Device Architecture", in IEEE Transactions on Electron Devices, 2022.

  2. S. Chen#,J. Liang#,(共同一作)et al. and G. Xiao, " Enabling UTBB Strained SOI Platform for Co-integration of Logic and RF: Implant-Induced Strain Relaxation and Comb-like Device Architecture," in Symp. on VLSI Tech.2020, USA, Jun. 14-19, 2020.

  3. J. Liangand A. Todri-Sanial, "Importance of Interconnects: A Technology System-Level Design Perspective," in IEEE International Electron Devices Meeting(IEDM), San Francisco, December, 19377637,2019.

  4. J. Liang, Rongmei Chen, et al., and A. Todri-Sanial*, "Investigation of Pt-Salt Doped Stand-Alone Multi-Wall Carbon Nanotubes for On-Chip Interconnect Applications," in IEEE Transactions on Electron Devices, 66, 2346-2352,2019.

  5. J. Liang, Jaehyun Lee, et al., and A. Todri-Sanial*, "Atomistic to Circuit-Level Modeling of Doped SWCNT for On-Chip Interconnects," in IEEE Transactions on Nanotechnology, 17, 1084-1088,2018.

  6. J. Liang, et al., and A. Todri-Sanial*, "A Physics-Based Investigation of Pt-Salt Doped Carbon Nanotubes for Local Interconnects," in IEEE International Electron Devices Meeting (IEDM), San Francisco, December, 35.5.1-35.5.4,2017.

  7. J. Liang, et al., "Atomistic to Circuit Level Modeling of Defective Doped SWCNTs with Contacts for On-Chip Interconnect Application,” in IEEE Nanotechnology Materials and Devices Conference (NMDC), Singapore, October 2017, pp. 66-67.

  8. S. Chen, H. Xu,J. Liang, et al. and G. Xiao*, " Strained Silicon-on-Insulator Platform for Cointegration of Logic and RF—Part I:Implant-Induced Strain Relaxation," IEEE Transactions on Electron Devices, 2021,vol. 68, pp 1425-1431.

  9. R. Chen , L. Chen,J. Liang, et al. , A. Asenov, and A. Todri-Sanial, "Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part I: CNFET Transistor Optimization," in IEEE Transactions on Very Large Scale Integration (VLSI) System, 2022, pp 1-8, Early Access.

  10. R. Chen , L. Chen,J. Liang, et al. , A. Asenov, and A. Todri-Sanial, "Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation—Part II: CNT Interconnect Optimization," in IEEE Transactions on Very Large Scale Integration (VLSI) System, 2022, pp 1-9, Early Access.

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